![]() ![]() ![]() 6 Field-Effect Transistors IG = 0 A, ID = IDSS(1 - VGS>VP)2, ID = IS, VGS = VP (1 - 2ID >IDSS), ID = IDSS >4 (if VGS = VP>2), ID = IDSS >2 (if VGS ⬵ 0.3 VP), PD = VDSID, rd = ro >(1 - VGS>VP)2 MOSFET: ID = k(VGS - VT)2, k = ID(on) >(VGS(on) - VT)2 7 FET Biasing Fixed-bias: VGS = - VGG, VDS = VDD - IDRD self-bias: VGS = - IDRS, VDS = VDD - ID(RS + RD), VS = IDRS voltage-divider: VG = R2VDD>(R1 + R2), VGS = VG - ID RS, VDS = VDD - ID(RD + RS) common-gate configuration: VGS = VSS - IDRS, VDS = VDD + VSS - ID(RD + RS) special case: VGSQ = 0 V: IIQ = IDSS, VDS = VDD - IDRD, VD = VDS, VS = 0 V. , PD = VD ID, TC = (⌬VZ >VZ)>(T1 - T0) * 100%>⬚C 2 Diode Applications Silicon: VK ⬵ 0.7 V, germanium: VK ⬵ 0.3 V, GaAs: VK ⬵ 1.2 V half-wave: Vdc = 0.318Vm full-wave: Vdc = 0.636Vm 3 Bipolar Junction Transistors IE = IC + IB, IC = ICmajority + ICOminority, IC ⬵ IE, VBE = 0.7 V, adc = IC>IE, IC = aIE + ICBO, aac = ⌬IC >⌬IE, ICEO = ICBO >(1 - a), bdc = IC>IB, bac = ⌬IC >⌬IB, a = b>(b + 1), b = a>(1 - a), IC = bIB, IE = (b + 1)IB, PCmax = VCEIC 4 DC Biasing-BJTs In general: VBE = 0.7 V, IC ⬵ IE, IC = bIB fixed-bias: IB = (VCC - VBE)>RB,VCE = VCC - ICRC, ICsat = VCC>RC emitter-stabilized: IB = (VCC - VBE)>(RB + (b + 1)RE), Ri = (b + 1)RE, VCE = VCC - IC(RC + RE), ICsat = VCC >(RC + RE) voltage-divider: exact: RTh = R1 储 R2, ETh = R2VCC >(R1 + R2), IB = (ETh - VBE)>(RTh + (b + 1)RE), VCE = VCC - IC(RC + RE), approximate: bRE Ú 10R2, VB = R2VCC >(R1 + R2), VE = VB - VBE, IC ⬵ IE = VE >RE voltage-feedback: IB = (VCC - VBE)>(RB + b(RC + RE)) common-base: IB = (VEE - VBE)>RE switching transistors: ton = tr + td, toff = ts + tf stability: S(ICO) = ⌬IC >⌬ICO fixed-bias: S(ICO) = b + 1 emitter-bias: S(ICO) = (b + 1)(1 + RB >RE)>(1 + b + RB >RE) voltage-divider: S(ICO) = (b + 1)(1 + RTh >RE)>(1 + b + RTh >RE) feedback-bias: S(ICO) = (b + 1)(1 + RB>RC)>(1 + b + RB>RC), S(VBE) = ⌬IC >⌬VBE fixed-bias: S(VBE) = - b>RB emitter-bias: S(VBE) = - b>(RB + (b + 1)RE) voltage-divider: S(VBE) = - b>(RTh + (b + 1)RE) feedback bias: S(VBE) = - b>(RB + (b + 1)RC), S(b) = ⌬IC >⌬b fixed-bias: S(b) = IC1 >b1 emitter-bias: S(b) = IC1(1 + RB>RE)> (b1(1 + b2 + RB>RE)) voltage-divider: S(b) = IC1(1 + RTh >RE)>(b1(1 + b2 + RTh >RE)) feedback-bias: S(b) = IC1(1 + RB >RC)>(b1(1 + b2 + RB >RC)), ⌬IC = S(ICO) ⌬ICO + S(VBE) ⌬VBE + S(b) ⌬b 5 BJT AC Analysis re = 26 mV>IE CE fixed-bias: Zi ⬵ bre, Zo ⬵ RC, Av = - RC>re voltage-divider bias: Zi = R1 储 R2 储 bre, Zo ⬵ RC, Av = - RC>re CE emitter-bias: Zi ⬵ RB 储 bRE, Zo ⬵ RC, Av ⬵ - RC>RE emitter-follower: Zi ⬵ RB 储 bRE, Zo ⬵ re, Av ⬵ 1 common-base: Zi ⬵ RE 储 re, Zo ⬵ RC, Av ⬵ RC>re collector feedback: Zi ⬵ re >(1>b + RC>RF), Zo ⬵ RC 储 RF, Av = - RC>re collector dc feedback: Zi ⬵ RF1 储 bre, Zo ⬵ RC 储 RF2, Av = - (RF2 储 RC)>re effect of load impedance: Av = RLAvNL >(RL + Ro), Ai = - Av Zi >RL effect of source impedance: Vi = RiVs>(Ri + Rs), Avs = Ri AvNL >(Ri + Rs), Is = Vs>(Rs + Ri) combined effect of load and source impedance: Av = RLAv NL >(RL + Ro), Avs = (Ri >(Ri + Rs))(RL >(RL + Ro))AvNL, Ai = - Av Ri >RL, Ais = - Avs(Rs + Ri)>RL cascode connection: Av = Av1Av2 Darlington connection: bD = b1b2 emitter-follower configuration: IB = (VCC - VBE)>(RB + bDRE), IC ⬵ IE ⬵ bDIB, Zi = RB 储 b1b2RE, Ai = bDRB >(RB + bDRE), Av ⬵ 1, Zo = re1>b2 + re2 basic amplifier configuration: Zi = R1 储 R2 储 Zi⬘, Zi⬘ = b1(re1 + b2re2), Ai = bD(R1 储 R2)>(R1 储 R2 + Zi⬘), Av = bDRC>Zi⬘, Zo = RC 储 ro2 feedback pair: IB1 = (VCC - VBE1)>(RB + b1b2RC), Zi = RB 储 Zi⬘, Zi⬘ = b1re1 + b1b2RC, Ai = - b1b2RB >(RB + b1b2RC) Av = b2RC >(re + b2RC) ⬵ 1, Zo ⬵ re1 >b2. ![]()
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